1. Field of the Invention
The present invention relates to an address pointer for designating an address in a semiconductor memory device, and particularly to an address pointer in a semiconductor memory device in which addresses are sequentially designated. More particularly, the invention relates to a construction of an address pointer for sequentially designating row addresses in a sequentially accessible semiconductor memory device.
2. Description of the Background Art
In devices such as TV receivers, facsimile transmitting/receiving devices and copying machines, in which image information is subjected to digital processing, semiconductor memory devices have been widely used as buffer memories. In these applications, image information is sequentially supplied to a buffer memory regardless of its type, i.e., still image information or dynamic image information. The semiconductor memory device sequentially stores the applied information. In many semiconductor memory devices used for such application, counters have been used as address pointers for designating addresses in order to achieve high-speed access. The semiconductor memory devices in which the addresses are selected in a sequential order are called sequential access memories (will be called "SAMs" hereinafter).
FIG. 20 schematically shows an overall construction of a conventional SAM. Referring to FIG. 20, the SAM includes a memory cell array 4 including a plurality of memory cells which are arranged in a matrix of rows and columns, a row address pointer 10 for selecting the memory cells at one row in memory cell array 4, and a column address pointer 11 for setting the memory cells at one column in memory cell array 4 at a selected state. If one word in memory cell array 4 has multiple bits, a column selecting signal supplied from column address pointer 11 sets one word at the selected state.
The SAM further includes a buffer circuit 20 which generates an internal reset signal in response to a reset signal RST. Buffer circuit 20 includes an inverter circuit 20a for generating a complementary internal reset signal /RST which is an inversion of a reset signal RST, and inverter circuits 20b and 20c which are cascadedly connected in two stages for buffer processing of reset signal RST.
Row address pointer 10 includes a node RH for receiving the complementary internal reset signal /RST from buffer circuit 20, a node RL for receiving the internal reset signal RST from buffer circuit 20, a node R.phi. for receiving a row selecting clock signal R.phi. which provides a row selecting timing of memory cell array 4, and output nodes RO(0) through RO(-1) which are sequentially set at the selected state in response to the row selecting clock signal R.phi..
Output nodes RO(0) through RO(N-1) of row address pointer 10 are arranged corresponding to the rows in memory cell array 4. Specifically, output nodes RO(0) through RO(N-1) of row address pointer 10 correspond to respective row selecting signal lines, each of which selects the memory cells at one row in memory cell array 4. Row address pointer 10 sequentially selects output nodes RO(0) through RO(N-1) in response to the row selecting clock signal R.phi., whereby the corresponding rows in memory cell array 4 are sequentially selected.
Row address pointer 10 further includes a node C.phi.O which supplies a shift clock signal C.phi.O after the output node RO(N-1) is selected. Shift clock signal C.phi.O is applied to a clock signal input node C.phi.1 of column address pointer 11.
Column address pointer 11 includes output nodes CO(0) through CO(N-1) arranged corresponding to respective columns in memory cell array 4, and reset nodes RH and RL which receive, respectively, a complementary internal reset signal /RST and an internal reset signal RST from buffer circuit 20. Column address pointer 11 shifts a selected output node by one to the adjacent output node each time the clock signal is applied to the clock input node C.phi.I.
The SAM shown in FIG. 20 may be formed of a dedicated one chip, or may be integrated with other data processing device(s) on a common chip. In the latter case, the reset signal RST and the row selecting clock signal R.phi. are transmitted from a control circuit formed on the same chip. Now, an operation will be briefly described below. When the reset signal RST which is an "L" active signal is activated, row address pointer 10 and column address pointer 11 are initialized. Specifically, when the reset signal RST goes to "L", the row address pointer 10 and the column address pointer 11 select output node RO(0) and CO(0), respectively.
Upon each application of row selecting clock signal R.phi., row address pointer 10 shifts by one the position of its selected output node. Thereby, the memory cells at the same column but at the different rows are sequentially selected, and information is written into or read from the selected memory cells. After the final output node RO(N-1) is selected in the row address pointer 10, shift clock signal C.phi.O is generated and applied to the column address pointer 11.
Column address pointer 11 shifts by one the position of the selected output node in synchronization with the change of output node RO(N-1) in row address pointer 10 into the unselected state. Thereby, the memory cells in the next column are sequentially selected, starting from the first row, and the access to the selected memory cells is performed. The operation continues as long as the clock signal R.phi. is applied. In the SAM, selection of the rows and columns in memory cell array 4 is carried out in response to the row selecting signal R.phi. and the shift clock signal C.phi.O, as described above. Therefore, it does not require control signals such as a row address strobe signal /RAS, a column address strobe signal /CAS and a chip selecting signal /CS for taking in an address, which allows high-speed access and thus the processing of the image information at higher speed.
Data is written in or read from sequentially selected memory cells in memory cell array 4 through an I/O circuit 21.
FIG. 21 shows an example of a construction of the memory cell array 4 shown in FIG. 20. In FIG. 21, memory cell array 4 includes a plurality of memory cells arranged in a matrix of rows and columns. FIG. 21 representatively shows memory cells arranged in two rows by two columns in a word unit. Memory cells on one row are associated with one row selecting line RO. Memory cells (a word unit) in one column are related to one column selecting line CO. For the memory cells of the respective word units, there are provided AND circuits each for receiving a row selecting signal on the associated row selecting line and a column selecting signal on the associated column selecting line. Specifically, AND circuits AN1 and AN2 are disposed corresponding to respective points at which the row selecting line RO(i) intersects the column selecting lines CO(j) and CO(j+1). AND circuits AN3 and AN4 are disposed corresponding to the points at which the row selecting line RO(i+1) intersects the column selecting lines CO(j) and CO(j+1).
AND circuit AN1 selects the corresponding memory cells MWij of one word when corresponding row selecting line RO(i) and column selecting line CO(j) are selected. AND circuit AN2 selects memory cells MWi(j+1) of one word when row selecting line RO(i) and column selecting line CO(j+1) are selected.
In a similar manner, AND circuits AN3 and AN4 select memory cells MW(i+1)j of one word and memory cells MW(i+1)(j+1) of one word when row selecting line RO(i+1) and column selecting lines CO(i) and CO(j+1) are selected, respectively.
Provision of AND circuits at the respective intersections of the row selecting lines RO and column selecting lines CO ensures the selection of only the memory cells of one word, and prevents undesired writing and reading of data.
The memory cells may be dynamic type memory cells, and also may be static type memory cells. Selected memory cells of one word are connected to internal data lines IOa, IOb and IOc, which in turn are connected to I/O circuit 21.
As shown in FIG. 21, when the memory cells are accessed in word units, the addresses are allocated in memory cell array 4 as shown in FIG. 22.
Referring to FIG. 22, the memory cell array 4 includes the memory cells disposed in N rows and M columns. The memory cells of one word are connected at one column. In this arrangement, the memory cell at address (0, 0) in the memory cell array 4 is first selected, and then the memory cells at the addresses (1, 0), . . . , (N-1, 0) are sequentially selected. After the selection of the memory cells (word unit) in the 0th column, the access starts from the memory cell at the 0th row in the first column. Finally, the memory cells (one word) at the (N-1)th row and (M-1)th column are accessed, and then the memory cells at the 0th row and 0th column are accessed again.
FIG. 23 is a block diagram showing a construction of the row address pointer shown in FIG. 20. In FIG. 20, the row address pointer 10 includes cascadedly connected shift registers 9A and 9B1-9B(N-1) at N stages. Shift register 9A at a first stage is reset to "1" in response to the reset signals applied to reset nodes RH and RL. Shift registers 9B(1)-9B(N-1) is reset to "0" in response to reset signal RL. In the following description, each node and each signal applied thereto are designated by the same reference character.
Each of shift registers 9A and 9B1-9B(N-1) includes an input node SI, an output node SO and clock input nodes .phi. and /.phi.. Each of shift registers 9A and 9B1-9B(N-1) performs a shift operation in response to clock signals R.phi. and /R.phi. of two phases. Specifically, each shift register is responsive to clock signal R.phi. to latch the applied signal, and is responsive to clock signal /R.phi. to output the latched signal. Row selecting signals for selecting row selecting lines RO(0)-RO(N-1) are supplied from output nodes SO of shift registers 9A and 9B1-9B(N-1), respectively.
Output node SO of shift register 9B(N-1) at the final stage in row address pointer 10 is coupled to the input node SI of shift register 9A at the first stage through drive circuits DV1 and DV2 in an even number of stages. Due to this ring configuration, rows in the memory cell array are repeatedly and sequentially selected. Drive circuits DV1 and DV2 are provided for reducing the delay in signal transmission from the final shift register 9B(N-1) to the first shift register 9A, and have different driving capabilities with each other. Specifically, drive circuit DV2 has the driving capability larger than that of drive circuit DV1. Final shift register 9B(N-1) also generates shift clock signal C.phi.0 to be applied to column address pointer 11.
Row address pointer 10 also includes inverter circuits IV1, IV2 and IV3 for generating internal clock signals R.phi. and /R.phi. in response to row selecting clock signal R.phi. applied to clock input node R.phi.I. Inverter circuits IV1 and IV2 are cascadedly connected to generate the clock signal R.phi.. Inverter circuit IV3 inverts the clock applied to the node R.phi.I to produce the complementary clock signal /R.phi..
FIG. 24 shows an example of a construction of the column address pointer shown in FIG. 20. In FIG. 24, column address pointer 11 has a construction similar to that of row address pointer 10 shown in FIG. 23, and it includes shift registers which are cascadedly connected in M stages. Constructions of these shift registers 9A and 9B1-9B(M-1) are similar to those of shift registers 9A and 9B1-9B(N-1) shown in FIG. 23, except that clock signals applied to clock input nodes .phi. and /.phi. are not the signals R.phi. and /R.phi. but the clock signals C.phi. and /C.phi. which in turn are generated in response to shift clock signal C.phi.O supplied from row address pointer 10. Column selecting signals CO(0)-CO(M-1) for selecting the respective column selecting lines are supplied from output nodes SO of shift registers 9A and 9B1-9B(M-1).
Also in column address pointer 11, the output node SO of the final shift register 9B(M-1) is coupled to the input node SI of the first shift register 9A through drive circuits DV3 and DV4 which are cascadedly connected in two stages. Drive circuits DV3 and DV4 are inverter circuits, and can transmit the output of the final shift register 9B(M-1) to the input node SI of the first shift register 9A at high speed.
Column address pointer 11 further includes inverter circuits IV4, IV5 and IV6 for generating clock signals C.phi. and /C.phi. of two phases in response to shift clock signal C.phi.O. Inverter circuits IV4 and IV5 are cascadedly connected to generate clock signal C.phi.. Inverter circuit IV6 inverts the signal applied to the input node C.phi.I to form the complementary clock signal /C.phi.. Now, operations of row and column address pointers shown in FIGS. 23 and 24 will be described below with reference to a waveform diagram of FIG. 25.
First, reset signal RST is generated, so that an initial value of shift register 9A at the first stage of row address pointer 10 is set at "1", and initial values of the other shift registers 9B1-9B(N-1) are set at "0". The value of "1" which is initially set in the first shift register 9A in row address pointer 10 is output in response to the falling of row selecting clock signal R.phi.. In response to this falling of the clock signal R.phi., row selecting signal R(0) is generated. Meanwhile, reset signal RST is also applied to column address pointer 11, so that the initial value of the first shift register 9A in the column address pointer is set at "1" and initial values of the other shift registers 9B1-9B(M-1) are set at "0". Therefore, only column selecting line CO(0) is set at the selected state by column address pointer 11.
The clock signal for column address pointer 11 is formed by the shift clock signal C.phi.O supplied from row address pointer 10. Therefore, until row address pointer 10 generates shift clock signal C.phi.O, the shift operation is not performed in column address pointer 11, and column selecting line CO(0) is kept in the selected state. When all the rows at the 0th column are sequentially set at the selected state, shift clock signal C.phi.O is generated by the final shift register 9B(N-1) in row address pointer 10. Shift clock signal C.phi.O is applied to column address pointer 11, which performs the shift operation in response to the falling of the shift clock signal C.phi.O to set the adjacent column selecting signal CO(1) at the selected state. Thereafter, the above operation is repeated, and finally, column selecting line CO(N-1) is selected.
When the output at the final stage in row address pointer 10 changes from "1" to "0", output CO(0) of the first shift register 9A in column address pointer 11 goes to "0", and output CO(1) of the next adjacent shift register 9B1 goes to "1". This operation is repeated, so that the respective words in memory cell array 4 are sequentially selected.
In column address pointer 11 shown in FIG. 24, shift clock signals C.phi. and /C.phi. are generated in response to the shift clock signal C.phi.o supplied from row address pointer 10. Shift clock signal C.phi.o is generated when all the rows at one column are selected by row address pointer 10, i.e., when output RO(N-1) is generated from the final shift register 9B(N-1) in the row address pointer 10. In this case, column selecting line CO(0) may not be selected in response to reset signals RH and RL at the initial state of column address pointer 11 (if row and column address pointers 10 and 11 have the same construction). This can be prevented using the structure shown in FIG. 26 by applying to column address pointer 11 a shift clock signal formed by AND processing of a delayed falling signal of the reset signal RST and column selecting clock signal R.phi.. That is, in FIG. 26, the structure includes a delay circuit 400 for delaying only the falling of the reset signal RST, an AND circuit 402 for taking a logical product of an output of the delay circuit 400 and the clock signal R.phi., and an OR circuit 404 for taking a logical sum of an output of AND circuit 402 and the shift clock signal C.phi.O. The delay circuit 400 includes cascaded inverters 410 and 412 for delaying the reset signal RST, and an OR circuit 414 receiving an output of the inverter 412 and the reset signal RST. Now, operation of the structure of FIG. 26 will be described with reference to the operating waveform diagram of FIG. 27.
The reset signal RST has only the falling delayed by the delay circuit 400. More specifically, the reset signal RST is delayed by the cascaded inverters 410 and 412. OR circuit 414 produces an "H" signal when at least one of its inputs is at "H" level. Thus, the delay circuit 400 generates a delayed fall signal of the reset signal RST. When the delay period is appropriate such that the fall-delayed reset signal has active period ("H" period.) overlapping with the generation of a first shift clock signal R.phi., AND circuit 402 generates an active signal to allow OR circuit 400 to produce the shift clock signal C.phi.I.
As described above, by using the outputs of the shift registers as the signal for selecting a row and a column, each word in the memory cell array can be sequentially accessed at high speed. In order to achieve this sequential operation, the outputs of the final shift registers 9B(N-1) and 9B(M-1) in row and column address pointers 10 and 11 are returned to the first shift registers 9A through drive circuits DV1 and DV2 and drive circuits DV3 and DV4, respectively.
Drive circuits DV1-DV4 are employed for the following reason. As the memory capacity of the semiconductor memory device increases, the number of the rows and columns in the memory cell array increases. Row address pointer 10 and column address pointer 11 include the shift register stages of which numbers are equal to the numbers of the rows and columns in memory cell array 4, respectively. Therefore, with the increase of the memory capacity of the semiconductor memory device, a distance between the shift registers at the final and first stages in the row (column) address pointer increases. This increases a length of a signal line through which the output of the final shift register in the row (column) address pointer is fed back to the input of the first shift register, and thus causes delay of the signals due to R (interconnection resistance) and C (interconnection capacitance) to the signals transmitted therethrough.
Drive circuits DV1-DV4 are provided in order to minimize the signal propagation delay due to the RC delay in the signal lines for feed back. The drive circuits DV1 -DV4 are formed of inverter circuits having large driving capabilities (i.e., large transistor sizes). As the numbers of the rows and/or columns in the memory cell array increase, the distances between the outputs of the final shift registers and the inputs of the first shift registers in the address pointers increase, and thus drive circuits DV1-DV4 having larger driving capabilities are needed.
The drive circuits are generally formed of MOS (insulated gate type) transistors because of their low power consumption. If the transistor size is increased for increasing the driving capability of the drive circuit, an input gate capacitance (i.e., capacitance between source/drain and gate) increases. In order to achieve the high-speed driving of the large input capacitance, it is necessary to increase the driving capability of the final shift register in the row (column) address pointer. Therefore, the final shift register in the row (column) address pointer and the other shift registers must employ transistors having different sizes. This impairs regularity in the configuration of the semiconductor memory device. Generally, if the regularity of components is impaired in the configuration of the semiconductor memory device, efficient arrangement of the components becomes impossible, resulting in reduction of an area utilizing efficiency. The problem that the regularity is impaired will be specifically described below.
FIG. 28 shows a correspondence between the row address pointer and the memory cells. As shown in FIG. 28, row address pointer 10 is practically disposed in a central portion of the memory cell array 4. This arrangement is employed for shortening the row selecting lines so as to transmit a row selecting signal to the end of a selected row selecting line at high speed. Row address pointer 10 includes shift registers arranged in two lines. In the same figure, there are shown four shift registers 9B(N-4)--9B(N-1). The shift registers each are arranged in two lines to accord to a pitch of the memory cells.
If the final shift register 9B(N-1) had the transistor size larger than those of the other shift registers 9B(N-4)-9B(N-2), final shift register 9B(N-1) would protrude outside an area end A allotted to the semiconductor memory device, and this area end would be extended to an area end B in FIG. 28, resulting in increase of the area occupied by the semiconductor memory device.
In order to reduce the input gate capacitance of the drive circuit, the number of the stages of the drive circuit is made four or more, and the transistor sizes are made sequentially increased from the input stage to the output stage. (Generally, it has been known that if the driving capabilities of the drive circuits are increased with a certain ratio, the driving speed can be increased.) In FIGS. 23 and 24, driving circuits DV1 and DV3 and driving circuits DV2 and DV4 are shown having different transistor sizes.
In this construction, however, the delay time in the feed back from the final shift register in the row (column) address pointer to the initial shift register 9A cannot be reduced to zero. Since the final shift register 9B(N-1) or 9B(M-1) in the row (column) address pointer drives the drive circuit and also generates the row (column) selecting signal to drive the row (column) selecting line, these final shift registers 9B(N-1) and 9B(M-1) are required to have the driving capabilities larger than those of the other shift registers. Therefore, it is difficult to maintain the regularity in the configuration of the semiconductor memory device.